Carbon Nanotube Field Effect Transistor-Based Combinational Circuits

The aim of this paper is to design Carbon Nanotube Field Effect Transistor-based (CNTFET-based) combinational circuits with improved Power Delay Product (PDP). Ternary logic circuits have attracted substantial interest due to their capability of increasing information content per unit area. As a result, the geometry-dependent threshold voltage of CNTFETs is effectively used to design a ternary logic family. In this paper, two combinational circuits, Ternary Half Adder and One bit Ternary Multiplier are designed by combining the ternary and binary logic gates to take advantage of both design methods. The simulation results of the combinational circuits have been compared with the existing different designs for their performance. Power Delay Product (PDP) is used as a metric of comparison. Using HSPICE simulation, the PDP of the ternary half adder and ternary one bit multiplier is found to be 7.33*10-17 J and 4.21*10-17 J, respectively. These values are 6.17*10-15 J and 2.62*10-15, respectively for the existing CMOS based design. This shows CNTFET-based ternary logic design has tremendous amount of performance improvement.